Interrupts, memory and I/O interfacing notes — Unit 4

An interrupt is an external hardware signal or internal software instruction that forces the microprocessor to pause its current program and execute a special subroutine to handle an urgent event.

⇒1.1 Why Interrupts?

Without interrupts, a CPU must constantly ask devices 'Do you have data?' (Polling). Polling wastes massive amounts of processing time. With interrupts, the CPU ignores the keyboard until the keyboard sends an electrical signal shouting 'A key was pressed!', allowing the CPU to instantly react.

When a valid interrupt is received, the CPU follows a strict sequence:

• 1. It finishes the currently executing instruction. It does not stop midway.
• 2. It PUSHes the current Program Counter (the return address) onto the Stack.
• 3. It disables further interrupts (usually) to prevent being interrupted while handling the current one.
• 4. It loads the PC with the address of the Interrupt Service Routine (ISR).
• 5. It executes the ISR to handle the device.
• 6. The ISR ends with a `RET` (or `IRET`), popping the original PC from the stack and resuming the main program exactly where it left off.

The 8085 has five physical hardware interrupt pins on the chip. They have a strict priority system in case two interrupt simultaneously.

• 1. TRAP: Highest priority. Non-maskable (cannot be disabled by software). Used for catastrophic events like power failure.
• 2. RST 7.5: Maskable. Edge-triggered.
• 3. RST 6.5: Maskable. Level-triggered.
• 4. RST 5.5: Maskable. Level-triggered.
• 5. INTR: Lowest priority. Maskable. General-purpose interrupt request.

⇒4.1 Vectored Interrupts

The CPU automatically knows exactly where the ISR is stored in memory. The address (the 'vector') is hardcoded into the microprocessor's internal circuitry. TRAP, RST 7.5, 6.5, and 5.5 are vectored.

For example, when RST 7.5 goes high, the CPU automatically jumps to address `003CH`.

⇒4.2 Non-Vectored Interrupts

The CPU does not know where the ISR is. The interrupting external device must supply the address (or an instruction like `RST n`) via the data bus during the interrupt acknowledge cycle. INTR is the only non-vectored interrupt on the 8085.

Sometimes a critical block of code cannot be interrupted. Programmers can disable (mask) interrupts.

⇒5.1 Global Masking

The `DI` (Disable Interrupts) instruction turns off all maskable interrupts. `EI` turns them back on.

⇒5.2 Individual Masking

The 8085 uses the `SIM` (Set Interrupt Mask) instruction to individually enable or disable RST 7.5, 6.5, and 5.5. The programmer loads a specific bit pattern into the Accumulator and executes SIM. The `RIM` (Read Interrupt Mask) instruction reads the current mask status.

Microprocessors do not have enough internal memory to store programs. External memory chips (ROM and RAM) must be connected (interfaced) to the CPU.

⇒6.1 The Interface Requirements

To read from a memory chip, the CPU must provide three things:

• Address: Sent via the Address Bus to select the specific byte inside the memory chip.
• Data: Sent/Received via the Data Bus.
• Control Signals: The CPU must assert MEMR (Memory Read) or MEMW (Memory Write) to tell the chip whether to output data or accept data.

The 8085 has a 16-bit address bus (A0-A15). If we connect a small 2KB RAM chip, it only has 11 address pins (A0-A10, since 2^11 = 2048). What do we do with the remaining 5 CPU address pins (A11-A15)?

⇒7.1 Chip Select (CS)

Every memory chip has a Chip Select (CS) pin. The chip is entirely deactivated unless CS is pulled low (0V).

We use logic gates (Address Decoders, like a 3-to-8 decoder IC) connected to the upper address lines (A11-A15) to generate the CS signal. This maps the 2KB chip to a specific memory range (e.g., 2000H to 27FFH). If the CPU outputs address 4000H, the decoder ensures the chip remains deactivated.

Just like memory, peripheral devices (keyboards, displays) must be connected to the CPU. There are two architectures for addressing I/O devices.

⇒8.1 Memory-Mapped I/O

The I/O device is treated exactly like a memory chip. It is assigned a 16-bit address (e.g., 8000H). To send data to the printer, the CPU simply uses the `STA 8000H` (Store to Memory) instruction. Advantage: All memory instructions can be used on I/O. Disadvantage: Reduces the total available memory space.

⇒9.1 The Concept

The I/O devices have their own separate 8-bit address space, distinct from the 16-bit memory space. The 8085 can address 256 input ports and 256 output ports.

To talk to these devices, the CPU has a dedicated control pin `IO/M'`. When this pin is High, the CPU is talking to I/O. When Low, it is talking to Memory.

⇒9.2 Instructions

Memory-mapped I/O uses `LDA` and `STA`. Isolated I/O uses dedicated instructions:

• `IN 8-bit`: Reads data from the specified 8-bit port into the Accumulator.
• `OUT 8-bit`: Sends the Accumulator's data to the specified 8-bit port.

You cannot connect an LED directly to the CPU's data bus; the signals are too fast and electrical issues will occur. You must use an intermediary I/O chip. The Intel 8255 is the standard Programmable Peripheral Interface (PPI).

⇒10.1 Port Structure

The 8255 provides 24 I/O pins grouped into three 8-bit ports: Port A, Port B, and Port C (which can be split into two 4-bit ports).

It is 'Programmable' because software can configure each port to act as either an Input or an Output on the fly, without changing hardware wiring.

⇒11.1 BSR Mode (Bit Set/Reset)

Used exclusively to set or reset individual pins of Port C without affecting the other pins.

⇒11.2 I/O Modes

• Mode 0 (Simple I/O): Ports A, B, and C function as simple inputs or outputs with no handshaking (e.g., driving LEDs).
• Mode 1 (Handshake I/O): Ports A and B handle the data transfer, while Port C provides 'handshake' control signals (like 'Data Ready' and 'Acknowledge') to communicate with slow devices like printers.
• Mode 2 (Bidirectional): Port A acts as a bidirectional data bus, using Port C for handshaking.

The 8085 only has 5 interrupt pins. What if a PC needs to connect a keyboard, mouse, network card, sound card, hard drive, and serial port? The CPU doesn't have enough pins.

⇒12.1 Function of the 8259

The 8259 acts as an interrupt multiplexer. It accepts up to 8 external interrupt requests (IR0-IR7), resolves their priority, and sends a single interrupt signal (INTR) to the microprocessor.

When the CPU acknowledges the interrupt, the 8259 automatically places the correct vector address on the data bus, guiding the CPU to the correct ISR for the specific device that caused the interrupt.

Normally, to read a file from a hard drive into RAM, the Hard Drive sends a byte to the CPU, and the CPU writes the byte to RAM. For a 10 MB file, this wastes massive amounts of CPU time acting as a middleman.

⇒13.1 The DMA Concept

DMA allows high-speed I/O devices (like disk controllers) to read and write directly to the system RAM, bypassing the CPU entirely.

The DMA Controller (like the Intel 8237) sends a HOLD signal to the CPU. The CPU finishes its current instruction, disconnects itself from the Address and Data buses, and sends a HLDA (Hold Acknowledge) signal. The DMA controller takes control of the buses and blasts the 10 MB file straight into RAM at hardware speeds. Once done, it gives the buses back to the CPU.

A microprocessor's data bus is parallel (8 or 16 bits sent simultaneously over multiple wires). Parallel cables are expensive and suffer from interference over long distances. For long-distance communication (like internet or USB), data must be sent Serially (one bit at a time over a single wire).

⇒14.1 The 8251 USART

The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) bridges this gap.

• Transmission: It receives 8-bit parallel data from the CPU, adds start/stop bits, and converts it into a serial stream of bits to send over a cable.
• Reception: It receives a serial stream of bits from a cable, strips the start/stop bits, assembles them into an 8-bit parallel byte, and hands it to the CPU.