Instruction set and addressing modes — Unit 2 Notes (Microprocessors and Microcontrollers)

BCS605 · Unit 2

Instruction set and addressing modes notes — Unit 2

Free unit-wise study notes on instruction set and addressing modes for Microprocessors and Microcontrollers, Semester 6 of B.Tech — Computer Science & Engineering — key concepts, examples, important questions and a revision checklist for semester exams.

Instruction set and addressing modes

Notebook — 14 pages

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Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

1. Instruction Format

An instruction is a binary command given to the microprocessor to perform a specific operation on given data. A complete instruction consists of two parts: the Opcode and the Operand.

1.1 Opcode and Operand

  • Opcode (Operation Code): The part of the instruction that tells the processor what to do (e.g., ADD, SUB, MOV).
  • Operand: The data on which the operation is to be performed. This can be actual data, a register name, or a memory address.

Example: In `MOV A, B` (Move the contents of B into A), `MOV` is the opcode, and `A, B` are the operands.

Next — Instruction Word Size

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Page 2

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

2. Instruction Word Size

Instructions are stored in memory as bytes. Depending on the complexity of the operand, an instruction can occupy different amounts of memory.

2.1 Word Sizes (8085)

  • 1-Byte Instructions: The opcode and operand fit into a single byte. Both operands are usually internal registers. Example: `MOV A, B` (copy B to A).
  • 2-Byte Instructions: The first byte specifies the opcode, and the second byte specifies 8-bit data. Example: `MVI A, 32H` (Load immediate data 32H into Accumulator).
  • 3-Byte Instructions: The first byte specifies the opcode, and the next two bytes specify a 16-bit memory address. Example: `LDA 2000H` (Load Accumulator with data from memory location 2000H).

Next — Addressing Modes Overview

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Page 3

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

3. Addressing Modes Overview

Addressing modes refer to the various ways a microprocessor can locate the operand (data) specified in an instruction.

3.1 Why multiple modes?

Different modes provide flexibility and efficiency for programmers. Sometimes you want to load a constant number, sometimes you want to copy a register, and sometimes you want to step through an array in memory. Addressing modes dictate how the CPU hardware calculates the final memory location.

Next — Immediate Addressing

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Page 4

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

4. Immediate and Register Addressing

4.1 Immediate Addressing

The operand data is provided immediately within the instruction itself. The CPU doesn't have to look in a register or memory to find the data; it's right there in the instruction code.

Example: `MVI A, 05H` (Load 05H immediately into A). In 8086: `MOV AX, 1234H`.

4.2 Register Addressing

The operands are completely contained within internal CPU registers. This is the fastest executing mode because it requires no external memory access after the instruction is fetched.

Example: `MOV A, B` (Copy contents of register B into register A).

Next — Direct and Indirect Addressing

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Page 5

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B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

5. Direct and Indirect Addressing

5.1 Direct Addressing

The 16-bit (or 20-bit) memory address of the operand is explicitly written out within the instruction.

Example (8085): `LDA 4000H` (Go directly to memory address 4000H, grab the data, and put it in Accumulator).

5.2 Register Indirect Addressing

The instruction specifies a register pair (like HL) that contains the memory address of the data. This is crucial for pointers and arrays.

Example: `MOV A, M` (Move the data from the memory location whose address is currently stored in the HL register pair into A).

Next — 8086 Specific Addressing

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Page 6

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

6. 8086 Advanced Addressing Modes

The 8086 introduces more complex addressing modes to support high-level languages like C (which require arrays, structs, and stack variables).

6.1 Base Register Addressing

The offset address of the operand is given by the sum of the contents of a base register (BX or BP) and a constant displacement value.

Example: `MOV AX, [BX+04H]`. If BX contains 1000H, the CPU will fetch data from offset 1004H. Excellent for accessing structs.

Next — Indexed Addressing

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Page 7

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

7. 8086 Indexed Addressing Modes

7.1 Indexed Addressing

The offset address is the sum of an index register (SI or DI) and a constant displacement. Used for accessing arrays.

Example: `MOV AX, [SI+100H]`. If SI is used as an array index (e.g., i=5), 100H is the base address of the array.

7.2 Base Indexed Addressing

The offset address is the sum of a base register (BX/BP) AND an index register (SI/DI). Excellent for 2D arrays.

Example: `MOV AX, [BX+SI]`. The physical address is `DS * 16 + BX + SI`.

Next — Instruction Set: Data Transfer

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Page 8

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

8. Data Transfer Instructions

These instructions copy data from a source to a destination. They do NOT affect the flags.

8.1 Key 8085 Data Transfer Ops

  • `MOV Rd, Rs`: Copy from source register to destination register.
  • `MVI R, 8-bit`: Move immediate 8-bit data into a register.
  • `LXI Rp, 16-bit`: Load 16-bit immediate data into a register pair (e.g., `LXI H, 2000H`).
  • `LDA 16-bit`: Load Accumulator direct from memory.
  • `STA 16-bit`: Store Accumulator direct to memory.
  • `XCHG`: Exchange the contents of HL and DE register pairs.

Next — Arithmetic Instructions

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Page 9

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B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

9. Arithmetic Instructions

Perform addition, subtraction, increment, and decrement. These operations update the Status Flags (Zero, Carry, Sign, etc.).

9.1 Key 8085 Arithmetic Ops

  • `ADD R`: Add register R to the Accumulator. Result stored in A.
  • `ADI 8-bit`: Add immediate 8-bit data to Accumulator.
  • `SUB R`: Subtract register R from Accumulator.
  • `INR R`: Increment register R by 1.
  • `DCR R`: Decrement register R by 1.
  • `INX Rp`: Increment a 16-bit register pair (e.g., HL) by 1 (used for moving to the next memory address).

Next — Logical Instructions

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Page 10

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B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

10. Logical Instructions

Perform Boolean logic operations on a bit-by-bit basis. They update the flags.

10.1 Key 8085 Logical Ops

  • `ANA R`: Logical AND register R with Accumulator. Used to mask (clear) specific bits.
  • `ORA R`: Logical OR register R with Accumulator. Used to set specific bits.
  • `XRA R`: Logical XOR register R with Accumulator. `XRA A` is a common trick to quickly clear the accumulator to zero.
  • `CMA`: Complement (NOT) the Accumulator (1s complement).
  • `CMP R`: Compare register R with Accumulator. It performs an internal subtraction (`A - R`) to update the flags, but does not alter the contents of A.

Next — Branching Instructions

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Page 11

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

11. Branching Instructions

Change the normal sequential execution of the program. They alter the Program Counter (PC).

11.1 Unconditional Jump

`JMP 16-bit`: The program unconditionally jumps to the specified memory address.

11.2 Conditional Jumps

The processor checks the Flag register. If the condition is true, it jumps. If false, it ignores the instruction and continues sequentially.

  • `JZ 16-bit`: Jump if Zero flag is set (Z=1). (e.g., jump if previous subtraction resulted in zero).
  • `JNZ 16-bit`: Jump if Not Zero (Z=0).
  • `JC 16-bit`: Jump if Carry flag is set.
  • `JNC 16-bit`: Jump if No Carry.

Next — Subroutine Instructions

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Page 12

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B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

12. Subroutine Instructions (CALL and RET)

A subroutine is a reusable block of code (a function). When you jump to a subroutine, the processor must remember where it came from so it can return after the function ends.

12.1 The Process

  • `CALL 16-bit`: When executed, the processor pushes the current Program Counter (the return address) onto the Stack. It then loads the subroutine address into the PC and jumps there.
  • `RET`: Placed at the end of the subroutine. It pops the top two bytes from the Stack back into the Program Counter, causing execution to resume immediately after the original CALL instruction.

Next — Machine Control

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Page 13

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B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

13. Machine Control Instructions

These instructions alter the state of the microprocessor itself, rather than processing data.

13.1 Key Operations

  • `HLT`: Halt. The processor stops fetching instructions and enters a wait state until an interrupt or reset occurs. Used to end a program.
  • `NOP`: No Operation. The processor does absolutely nothing for 4 clock cycles and moves to the next instruction. Used to create precise time delays.
  • `EI / DI`: Enable / Disable Interrupts. Turns the microprocessor's ability to respond to external hardware interrupts on or off.

Next — 8086 Extensions

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Page 14

Wink Notes

B.Tech CSE — 6th Semester

Microprocessors and Microcontrollers

Unit - 2

14. 8086 Instruction Set Extensions

The 16-bit 8086 instruction set is vastly more powerful than the 8085.

14.1 Key Additions

  • Multiplication and Division: The 8086 has hardware `MUL` and `DIV` instructions. The 8085 had to do multiplication by writing a loop of repeated additions.
  • String Manipulation: Powerful instructions like `MOVSB` (Move String Byte) can copy entire blocks of memory automatically using the SI and DI index registers.
  • Loop Instructions: `LOOP label` automatically decrements the CX register and jumps if CX is not zero, perfectly mimicking a high-level `for` loop in hardware.

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