Sequential circuits, latches and flip-flops notes — Unit 4

Unlike combinational circuits, the output of a Sequential Circuit depends not only on the present inputs but also on the past history of inputs.

⇒1.1 The Role of Memory and Feedback

Sequential circuits require memory elements. This is achieved by taking the output of a combinational circuit and feeding it back into the input. This feedback loop allows the circuit to "remember" a state.

⇒1.2 Synchronous vs Asynchronous

• Synchronous: The state of the memory elements is updated only at discrete instants of time, controlled by a master signal called a Clock. Highly predictable and standard in all modern processors.
• Asynchronous: The state changes immediately when inputs change. No clock is used. Faster, but extremely difficult to design due to timing issues and race conditions.

A Clock is a periodic square wave signal that alternates continuously between 0 (LOW) and 1 (HIGH). It acts as the heartbeat of a synchronous digital system.

⇒2.1 Clock Edges and Levels

A clock pulse has defined regions:

• Positive Level: The duration when the clock is HIGH.
• Negative Level: The duration when the clock is LOW.
• Positive Edge (Rising Edge): The exact, instantaneous moment the clock transitions from LOW to HIGH.
• Negative Edge (Falling Edge): The instantaneous moment the clock transitions from HIGH to LOW.

The fundamental difference between Latches and Flip-Flops is how they respond to these clock regions.

Both are basic memory elements capable of storing 1 bit of data. The difference lies in their triggering mechanisms.

⇒3.1 Latches (Level-Triggered)

A Latch is transparent while the enable (or clock) signal is at an active level (e.g., HIGH). During this entire time, any change in the inputs will immediately flow through and change the output. It only "latches" and locks the data when the signal goes LOW.

⇒3.2 Flip-Flops (Edge-Triggered)

A Flip-Flop only reads its inputs and updates its output at the exact instant of a clock edge (either rising or falling). During the rest of the clock cycle, inputs can change wildly but the output will remain strictly locked. This prevents glitches from cascading through a system.

The most basic memory element, built using cross-coupled NOR gates (or NAND gates).

⇒4.1 NOR-based SR Latch Operation

Inputs: Set ($S$) and Reset ($R$). Outputs: $Q$ and $Q'$ (which must always be opposites).

• $S=0, R=0$: Memory State. The output $Q$ remains whatever it was previously.
• $S=1, R=0$: Set State. $Q$ is forced to 1.
• $S=0, R=1$: Reset State. $Q$ is forced to 0.
• $S=1, R=1$: Invalid / Forbidden. This forces both $Q$ and $Q'$ to 0, breaking the rule that they must be complements. If inputs return to 00 simultaneously, the final state is unpredictable (Race condition).

By adding edge-triggering circuitry to an SR Latch, we get an SR Flip-Flop.

⇒5.1 Characteristic Table

Defines the next state ($Q_{n+1}$) based on present state ($Q_n$) and inputs.

• S=0, R=0 $\to$ $Q_{n+1} = Q_n$ (No Change)
• S=0, R=1 $\to$ $Q_{n+1} = 0$ (Reset)
• S=1, R=0 $\to$ $Q_{n+1} = 1$ (Set)
• S=1, R=1 $\to$ Invalid

⇒5.2 Characteristic Equation

Derived from a K-Map of the characteristic table:
$Q_{n+1} = S + R'Q_n$
*(Constraint: $SR = 0$ must be maintained to avoid the invalid state).*

Designed to eliminate the invalid $S=1, R=1$ state. We simply tie the $S$ input to the $R$ input through an inverter. So $S=D$ and $R=D'$.

⇒6.1 Operation

Whatever data is on the $D$ input is transferred to the $Q$ output exactly at the clock edge.

• If $D=0$ at clock edge $\to$ $Q_{n+1} = 0$
• If $D=1$ at clock edge $\to$ $Q_{n+1} = 1$

Characteristic Equation: $Q_{n+1} = D$.

The D Flip-Flop is the fundamental building block of CPU registers and RAM. It simply delays the input by one clock cycle.

The JK Flip-Flop improves on the SR Flip-Flop. It behaves identically for $J$ (Set) and $K$ (Reset), but it solves the invalid $1,1$ state by defining a useful operation for it.

⇒7.1 Characteristic Table

• J=0, K=0 $\to$ $Q_{n+1} = Q_n$ (No Change)
• J=0, K=1 $\to$ $Q_{n+1} = 0$ (Reset)
• J=1, K=0 $\to$ $Q_{n+1} = 1$ (Set)
• J=1, K=1 $\to$ $Q_{n+1} = Q_n'$ (Toggle. The output flips to its opposite state).

Characteristic Equation: $Q_{n+1} = JQ_n' + K'Q_n$.

The JK Flip-Flop is considered the most versatile of all flip-flops.

A severe problem occurs in JK Latches (or level-triggered JK flip-flops) when $J=1$ and $K=1$.

⇒8.1 The Phenomenon

If $J=1$ and $K=1$, the output is supposed to toggle. However, if the clock pulse remains HIGH for longer than the propagation delay of the gates, the output will toggle, feed back into the input, toggle again, and continue oscillating (racing) between 0 and 1 until the clock goes LOW. The final state becomes completely unpredictable.

⇒8.2 Solutions

• Ensure the clock pulse duration is shorter than the gate propagation delay (impractical to manufacture reliably).
• Use edge-triggering instead of level-triggering.
• Use the Master-Slave configuration.

A hardware solution to the Race Around Condition. It consists of two cascaded JK Latches: a "Master" and a "Slave".

⇒9.1 Operation

The clock signal to the Slave is inverted.
- When the Clock is HIGH: The Master is active and reads the J/K inputs. The Slave is inactive, so the final output $Q$ does not change.
- When the Clock goes LOW: The Master becomes inactive, locking its data. The Slave becomes active and copies the Master's data to the final output $Q$.

Because the output only changes when the Master is locked out from reading new inputs, feedback oscillation is impossible. This effectively creates a negative-edge-triggered flip-flop.

A specialized flip-flop derived from the JK Flip-Flop by tying the J and K inputs together ($J = K = T$).

⇒10.1 Characteristic Table

• If $T = 0$, $Q_{n+1} = Q_n$ (Memory / Hold state).
• If $T = 1$, $Q_{n+1} = Q_n'$ (Toggle state).

Characteristic Equation: $Q_{n+1} = T \oplus Q_n$.

The T Flip-Flop is almost exclusively used in designing binary counters and frequency dividers. If T is held at 1, the output toggles on every clock edge, effectively dividing the clock frequency by 2.

A Characteristic table tells you the Next State if you know the inputs.
An Excitation Table works backwards: It tells you what Inputs you need to apply to achieve a desired state transition from $Q_n$ to $Q_{n+1}$.
Excitation tables are absolutely critical for designing counters.

⇒11.1 SR Excitation Table

$0 \to 0$: S=0, R=X (Don't care)
$0 \to 1$: S=1, R=0
$1 \to 0$: S=0, R=1
$1 \to 1$: S=X, R=0

⇒11.2 JK Excitation Table

$0 \to 0$: J=0, K=X
$0 \to 1$: J=1, K=X
$1 \to 0$: J=X, K=1
$1 \to 1$: J=X, K=0

(Notice the abundance of Don't Cares in the JK table. This is why JK flip-flops result in simpler logic gate designs for counters).

A common exam problem: Given one type of flip-flop, design the external combinational logic required to make it behave like a different type of flip-flop.

⇒12.1 General Conversion Procedure

Example: Convert an SR Flip-Flop into a D Flip-Flop.

• 1. Write the truth table for the target (D) flip-flop: Columns for $D$, $Q_n$, and desired $Q_{n+1}$.
• 2. Append columns for the inputs of the available (SR) flip-flop.
• 3. Use the Excitation Table of the available (SR) flip-flop to fill in the SR columns based on the transition from $Q_n$ to $Q_{n+1}$.
• 4. Draw K-Maps to find Boolean equations for $S$ and $R$ in terms of $D$ and $Q_n$.
• 5. Result: $S = D$, $R = D'$. Draw the circuit.

Standard flip-flop inputs (S, R, J, K, D, T) are Synchronous. Their effect is delayed until the next clock edge.

However, practical flip-flop ICs include two Asynchronous override pins: `Preset` (PR) and `Clear` (CLR).

• Preset (PR): When activated, it immediately forces the output $Q$ to 1, completely ignoring the clock and the synchronous inputs.
• Clear (CLR): When activated, it immediately forces the output $Q$ to 0, ignoring the clock.

These are usually active-low pins (they activate when fed a 0). They are crucial for initializing a digital system (like a CPU reset button) to a known starting state before the clock starts ticking.

Unit 4 introduces time and memory into digital logic.

⇒14.1 University Exam Checklist

• What is the difference between a Latch and a Flip-Flop? (Level vs Edge triggering).
• Draw the logic diagram of an SR Latch using NAND gates and explain its truth table.
• Explain the Race Around Condition in a JK flip-flop. How does the Master-Slave configuration resolve it?
• Derive the Characteristic Equation for the JK and T flip-flops.
• Write the Excitation Tables for SR, JK, D, and T flip-flops from memory.
• Convert a JK Flip-Flop into a T Flip-Flop using the systematic conversion procedure.

⇒14.2 Hardware/VLSI Interview Focus

• Setup and Hold Times: The input to a flip-flop must be stable slightly before the clock edge (Setup time) and remain stable slightly after (Hold time). Violating this causes Metastability.
• Why are D Flip-Flops the industry standard for CPU registers rather than JK flip-flops?