Registers, counters and memory devices notes — Unit 5

A single flip-flop can store 1 bit of information. A Register is a group of $n$ flip-flops capable of storing an $n$-bit binary word.

Registers are the fastest memory locations in a computer system, located directly inside the CPU.

⇒1.1 Basic Data Movement

Data can be loaded into or read from a register in two ways:

• Serial: Data is moved one bit at a time, requiring $n$ clock cycles for an $n$-bit word. Saves hardware pins/wires, but is slow.
• Parallel: All $n$ bits are moved simultaneously in a single clock cycle. Requires more hardware wiring, but is extremely fast.

A Shift Register is a type of register that can shift its stored data left or right upon receiving a clock pulse. They are built by cascading D Flip-Flops (the $Q$ output of one is tied to the $D$ input of the next).

⇒2.1 The Four Modes of Operation

• SISO (Serial-In, Serial-Out): Data enters 1 bit at a time, and exits 1 bit at a time. Used for introducing a time delay in a digital signal.
• SIPO (Serial-In, Parallel-Out): Data enters 1 bit at a time, but all bits can be read simultaneously at the end. Used to convert serial communications (like USB) into parallel data for the CPU.
• PISO (Parallel-In, Serial-Out): All data is loaded instantly, then shifted out 1 bit at a time. Used to convert parallel CPU data into a serial stream for transmission over a network.
• PIPO (Parallel-In, Parallel-Out): Standard data register. Loads all bits instantly, reads all bits instantly. No shifting occurs.

A Universal Shift Register is a bidirectional register capable of operating in all four modes (SISO, SIPO, PISO, PIPO) and shifting in both directions.

⇒3.1 Construction

It is built using D Flip-Flops combined with Multiplexers at the input of each flip-flop. The multiplexers act as routers, controlled by Mode Control pins.

• Mode 00: Hold previous state.
• Mode 01: Shift Right.
• Mode 10: Shift Left.
• Mode 11: Parallel Load.

This IC (like the 74194) is a highly versatile building block in digital hardware.

A Counter is a specialized sequential circuit that progresses through a predefined sequence of states upon the application of clock pulses.

⇒4.1 Modulus of a Counter

The Modulus (MOD) of a counter is the total number of unique states it cycles through before resetting to its initial state.

An $n$-bit counter uses $n$ flip-flops and can have a maximum MOD of $2^n$. E.g., A 3-bit counter counts from 000 to 111 (MOD-8).

⇒4.2 Counter Classification

Counters are broadly classified by how the clock signal is routed:

• Asynchronous (Ripple) Counters: Only the first flip-flop receives the external clock. Subsequent flip-flops are clocked by the output of the preceding one.
• Synchronous Counters: The external clock is fed simultaneously to the clock pins of every flip-flop.

In a Ripple Counter, usually constructed from T flip-flops (or JK tied to 1), the external clock triggers only the LSB flip-flop.

⇒5.1 Mechanism

When $FF_0$ (LSB) toggles from 1 to 0 (a negative edge), its output acts as the clock pulse for $FF_1$, causing $FF_1$ to toggle. The signal "ripples" through the counter from LSB to MSB.

⇒5.2 Up vs Down Ripple Counters

• Up Counter: Uses Negative-edge triggered FFs, with $Q$ output connected to the next clock.
• Down Counter: Uses Positive-edge triggered FFs with $Q$ connected, OR Negative-edge FFs with $Q'$ connected to the next clock.

⇒5.3 The Ripple Delay Problem

Because the clock must propagate physically through each gate, the total delay is $n \times t_p$ (where $t_p$ is one flip-flop's delay). If the clock frequency is too high, the LSB might change again before the MSB has even received the first toggle command, causing erroneous state readings.

What if we want a counter that counts from 0 to 9 and then resets (a Decade or MOD-10 counter)? A 4-bit counter naturally counts to 15.

⇒6.1 Asynchronous Truncation

We use the Asynchronous Clear (CLR) pin on the flip-flops to force a reset before the natural count finishes.

• 1. Find the binary representation of the desired MOD $N$. For MOD-10, $N=10 = 1010_2$.
• 2. Identify which bits are '1' at this state. In $1010_2$, $Q_3$ and $Q_1$ are '1'.
• 3. Connect $Q_3$ and $Q_1$ into a NAND gate.
• 4. Connect the output of the NAND gate to the active-low CLR pins of all flip-flops.

When the counter hits 10 (1010), the NAND gate outputs a 0, instantly clearing all flip-flops back to 0000.
Note: The state '10' exists for a few nanoseconds (a glitch) before the clear takes effect. This is a flaw of asynchronous design.

To solve the ripple delay problem, Synchronous Counters apply the master clock to all flip-flops simultaneously. All state changes happen at the exact same instant.

⇒7.1 The Trade-off

Because all FFs receive the clock, we must use complex combinational logic at the J/K inputs to control which flip-flops are allowed to toggle on the next clock pulse.

⇒7.2 Logic for Synchronous Up Counter

• $FF_0$ (LSB): Toggles every clock pulse. ($J_0=1, K_0=1$).
• $FF_1$: Toggles only when $Q_0=1$. ($J_1=Q_0, K_1=Q_0$).
• $FF_2$: Toggles only when both $Q_0$ AND $Q_1$ are 1. ($J_2=Q_0Q_1, K_2=Q_0Q_1$).

This logic ensures the counter counts $000 \to 001 \to 010 \to 011$, etc.

Designing a synchronous counter for an arbitrary sequence (e.g., a Gray code counter or a random sequence 0, 3, 5, 2, 0) follows a strict, formal procedure.

⇒8.1 Five-Step Design Procedure

• 1. State Diagram & Number of FFs: Draw the required state transition sequence. Determine $n$ where $2^n \ge$ number of unique states.
• 2. Select Flip-Flop Type: Usually JK or T flip-flops.
• 3. State Transition Table: Create a table listing the Present State ($Q_n$) and the desired Next State ($Q_{n+1}$).
• 4. Excitation Table: Use the chosen flip-flop's excitation table to determine the necessary inputs (J, K) required to force each transition from $Q_n$ to $Q_{n+1}$. Add these as columns.
• 5. K-Map Minimization: Draw a K-Map for every single input (e.g., $J_0, K_0, J_1, K_1$) based on the Present State variables. Find the minimized Boolean equations.
• 6. Logic Diagram: Draw the final circuit connecting the clock, FFs, and the derived logic gates.

Specialized counters built by taking a shift register and feeding the final output back into the input.

⇒9.1 Ring Counter

A circular shift register. The $Q$ output of the last FF is connected to the $D$ input of the first FF.

• Must be pre-loaded with a single '1' (e.g., 1000).
• The '1' rotates: $1000 \to 0100 \to 0010 \to 0001 \to 1000$.
• Modulus: $n$ (An $n$-bit ring counter has $n$ states).
• Extremely inefficient in terms of states per flip-flop, but requires zero decoding logic.

⇒9.2 Johnson Counter (Twisted Ring)

The inverted output ($Q'$) of the last FF is connected to the $D$ input of the first FF.

• Starts at 0000. Fills with 1s from the left, then empties with 0s.
• Sequence: $0000 \to 1000 \to 1100 \to 1110 \to 1111 \to 0111 \to 0011 \to 0001 \to 0000$.
• Modulus: $2n$ (A 4-bit Johnson counter has 8 states).

While registers store small amounts of data directly in the CPU, main memory arrays store massive amounts of instructions and data.

⇒10.1 Memory Structure

A memory unit is specified as $2^k \times n$.

• $2^k$: The total number of addressable words (locations) in the memory. This requires a $k$-bit address bus.
• $n$: The size of each word in bits (e.g., 8-bit byte, 32-bit word). This requires an $n$-bit data bus.

Example: A $1024 \times 8$ memory has 1024 locations, each storing 1 byte. It requires 10 address lines ($2^{10} = 1024$) and 8 data lines.

RAM is volatile memory (loses data when power is removed). "Random Access" means any memory location can be accessed in the same amount of time, regardless of its physical position.

⇒11.1 Static RAM (SRAM)

Each bit is stored using a 6-transistor latch circuit (a flip-flop).

• Pros: Extremely fast. Data is stable as long as power is applied.
• Cons: Consumes more power, takes up more physical silicon space (lower density), very expensive.
• Use: CPU Cache (L1, L2, L3).

⇒11.2 Dynamic RAM (DRAM)

Each bit is stored as an electrical charge on a microscopic capacitor paired with a single transistor.

• Pros: Very high density (billions of bits per chip), cheap.
• Cons: Slower. Capacitors leak charge over time. The memory controller must constantly read and rewrite the data thousands of times per second (Refresh cycles), otherwise data is lost.
• Use: Main System Memory (DDR4, DDR5).

ROM is non-volatile memory (retains data without power). Historically read-only, modern variants can be rewritten.

⇒12.1 Types of ROM

• Mask ROM: Data is permanently etched into the silicon during semiconductor manufacturing. Cannot be changed.
• PROM (Programmable ROM): Blank when manufactured. The user writes data once using a high-voltage programmer that physically blows internal fuses.
• EPROM (Erasable PROM): Can be erased by exposing the silicon chip to strong Ultraviolet (UV) light through a quartz window on top of the IC.
• EEPROM (Electrically Erasable PROM): Can be erased and rewritten electronically, byte by byte, without removing it from the circuit.
• Flash Memory: A type of EEPROM that erases and writes in large blocks rather than byte-by-byte, making it much faster and cheaper. Used in SSDs and USB drives.

PLDs are generic ICs that can be programmed to implement any combinational logic circuit. They consist of an array of AND gates feeding into an array of OR gates (matching the SOP form).

⇒13.1 PLA, PAL, and ROM Arrays

• ROM as a PLD: The AND array is a fixed full decoder (generates all minterms). The OR array is programmable. (Used as look-up tables).
• PLA (Programmable Logic Array): Both the AND array and the OR array are programmable. Most flexible, but slower and more expensive.
• PAL (Programmable Array Logic): The AND array is programmable, but the OR array is fixed. Faster and cheaper than PLA, heavily used in early digital design.

Modern extensions of PLDs are CPLDs and FPGAs (Field Programmable Gate Arrays), which can simulate entire microprocessors in hardware.

This concludes Digital Logic Design. You now understand how transistors form gates, gates form flip-flops, and flip-flops form registers and memory.

⇒14.1 University Exam Checklist

• Explain the working of a 4-bit Universal Shift Register.
• Design a MOD-10 (Decade) Asynchronous Ripple Counter and explain the glitch that occurs at state 10.
• Use the 6-step formal design procedure to design a Synchronous Counter that counts the sequence $0 \to 3 \to 5 \to 7 \to 0$ using JK flip-flops.
• Compare Ring and Johnson counters. What is the modulus of a 5-bit Johnson counter?
• Differentiate between SRAM and DRAM in terms of construction, speed, density, and need for refresh.
• Explain the structural differences between PLA and PAL.

⇒14.2 Hardware/VLSI Interview Focus

• Why is Gray Code highly preferred for asynchronous FIFO queues spanning multiple clock domains? (Answer: Changing only one bit prevents false intermediate states during synchronization).
• How does setup/hold time violation manifest in a shift register?