Instruction set and CPU organisation notes — Unit 3

The Central Processing Unit (CPU) is the brain of the computer. Its primary job is to repeatedly fetch instructions from memory and execute them.

The collection of all different instructions that a CPU can execute is called its Instruction Set. The Instruction Set Architecture (ISA) serves as the boundary between hardware and software.

⇒1.1 Basic CPU Components

• Program Counter (PC): Holds the address of the next instruction to be fetched.
• Instruction Register (IR): Holds the instruction currently being executed.
• ALU: Performs data processing.
• General Purpose Registers (R0, R1...): Temporary fast storage for the programmer.
• Control Unit: Coordinates the above.

An instruction is a binary word. It is divided into fields:

• Opcode (Operation Code): Specifies the operation to be performed (e.g., ADD, LOAD, JUMP).
• Operand / Address Field: Specifies the data to be operated on, or the memory address where the data is located.
• Mode Field: Specifies how the operand field should be interpreted (Addressing Mode).

Computers are classified by how many addresses an instruction is allowed to specify.

⇒3.1 Three-Address Instructions

Format: `OPCODE Dest, Src1, Src2`
Example: `ADD R1, R2, R3` (Meaning: $R1 \leftarrow R2 + R3$)

• Requires a long instruction word (many bits needed to specify three registers/addresses).
• Results in very short, concise programs. Evaluating $X = (A+B) \times (C+D)$ takes very few instructions.

⇒3.2 Two-Address Instructions

Format: `OPCODE Dest, Src`
Example: `ADD R1, R2` (Meaning: $R1 \leftarrow R1 + R2$)

• One address acts as both a source and the destination. The original data in the destination is overwritten.
• The most common format in commercial computers (like x86).

⇒4.1 One-Address Instructions (Accumulator Org)

Format: `OPCODE Address`
Example: `ADD X` (Meaning: $AC \leftarrow AC + M[X]$)

• The CPU has only one main register, called the Accumulator (AC).
• The Accumulator is the implicit source and the implicit destination for all arithmetic. You don't need to name it in the instruction.

⇒4.2 Zero-Address Instructions (Stack Org)

Format: `OPCODE`
Example: `ADD` (Meaning: Pop top two values from stack, add them, push result back to stack).

• The CPU uses a Last-In-First-Out (LIFO) Stack.
• Instructions like `PUSH X` and `POP Y` are used to move data to/from memory. Math instructions require zero operands because they always operate implicitly on the Top of Stack (TOS).
• Programs are written using Reverse Polish Notation (Postfix).

The Addressing Mode determines how the CPU interprets the address field of the instruction to find the actual operand (the Effective Address).

Why have multiple modes?
1. To give programmers flexibility to handle arrays, pointers, and loops easily.
2. To reduce the number of bits in the instruction field.

⇒5.1 Implied Mode

The operand is specified implicitly in the definition of the instruction.
Examples: `CMA` (Complement Accumulator). The operand is obviously the Accumulator. No address field needed.

⇒5.2 Immediate Mode

The operand field contains the actual value to be used, not an address.
Example: `ADD #5` (Add the literal number 5 to the register). Used for initializing registers to constants.

⇒6.1 Direct Mode

The address field contains the exact physical memory address of the operand.
Example: `LOAD 1000`. (Go to memory location 1000, read the data, put it in the register).
Effective Address (EA) = Address field.

⇒6.2 Indirect Mode

The address field gives the memory address where a pointer to the operand is stored.
Example: `LOAD (1000)`. (Go to memory location 1000. Read the value there, say 5000. Now go to memory location 5000 and load that data).
EA = M[Address field].
Requires two memory accesses. Used heavily for passing pointers/references in C/C++.

⇒6.3 Register and Register Indirect

Same as above, but using CPU Registers instead of Memory.
Register Mode: `ADD R1` (Operand is in R1).
Register Indirect: `LOAD (R1)` (R1 holds the memory address of the operand).

These modes calculate the Effective Address by adding a value from a register to the address field in the instruction. $EA = A + (R)$.

⇒7.1 Relative Addressing Mode

The register used is the Program Counter (PC).
$EA = PC + A$.
Used for branch instructions (e.g., "Jump 5 lines forward"). Makes code position-independent (relocatable) because addresses are relative to where the code is currently executing.

⇒7.2 Indexed Addressing Mode

The register used is an Index Register (XR).
$EA = A + XR$.
Used for iterating through arrays. $A$ is the base address of the array, and $XR$ acts as the loop index ($i$), incrementing on each loop.

⇒7.3 Base Register Addressing

Similar to Indexed, but the Base Register holds a large memory address, and $A$ acts as a small offset. Used by Operating Systems to place user programs in different blocks of memory (segmentation).

A program consists of a sequence of instructions. The CPU executes each instruction through a rigid cycle of phases.

⇒8.1 The Standard Cycle

• 1. Fetch: Read the instruction from memory into the CPU.
• 2. Decode: The Control Unit determines what the instruction is.
• 3. Read Effective Address: If the instruction uses indirect addressing, fetch the actual operand address from memory.
• 4. Execute: Perform the operation.

This cycle repeats indefinitely until a `HALT` instruction is reached or power is removed.

Let's look at the exact hardware steps required just to fetch an instruction.

⇒9.1 Fetch Phase

Requires 3 clock cycles ($T_0, T_1, T_2$):

• $T_0: MAR \leftarrow PC$ (Move the address of the instruction into the Memory Address Register).
• $T_1: MDR \leftarrow M[MAR], PC \leftarrow PC + 1$ (Read the memory into MDR. Simultaneously, increment the PC to point to the next instruction).
• $T_2: IR \leftarrow MDR$ (Move the fetched instruction from MDR into the Instruction Register).

⇒9.2 Decode Phase

• $T_3:$ The opcode bits of IR are passed to the decoder. The addressing mode bit is evaluated.

From $T_4$ onwards, the timing signals diverge based on exactly which instruction was decoded.

An instruction set generally supports three main categories of operations.

⇒10.1 Data Transfer Instructions

Moves data between memory and registers without changing the data value.

• `LOAD` (Memory to Register), `STORE` (Register to Memory).
• `MOVE` (Register to Register).
• `PUSH` / `POP` (Stack operations).
• `IN` / `OUT` (I/O device operations).

⇒10.2 Data Manipulation Instructions

Perform computational capabilities. The ALU is active.

• Arithmetic: `ADD`, `SUB`, `MUL`, `DIV`, `INC`, `DEC`.
• Logical: `AND`, `OR`, `XOR`, `NOT`.
• Shift: `SHL` (Shift Left), `SHR`, `ROL` (Rotate Left).

By default, the CPU executes instructions linearly (PC increments by 1). Program Control instructions alter the PC, allowing loops, if-statements, and function calls.

⇒11.1 Branch / Jump

• Unconditional Branch (`JMP`): Always changes the PC to a new address.
• Conditional Branch (`JZ`, `JNZ`, `JC`): Changes the PC only if a specific condition is met (e.g., Jump if Zero flag is set). If not met, execution continues linearly.

⇒11.2 Subroutine Call and Return

Used for executing functions.

• `CALL`: Jumps to a function address, but FIRST saves the current PC (the return address) onto the Stack.
• `RETURN`: Pops the return address off the stack and loads it into the PC, resuming execution exactly where it left off before the `CALL`.

Conditional branches need to base their decisions on the results of the previous instruction. The CPU remembers these results using a special register called the Program Status Word (PSW) or Flags Register.

⇒12.1 Common Status Flags

• Z (Zero Flag): Set to 1 if the ALU output is exactly zero.
• S (Sign Flag): Set to 1 if the ALU output is negative (MSB is 1).
• C (Carry Flag): Set to 1 if an arithmetic operation generated a carry out of the MSB.
• V (Overflow Flag): Set to 1 if a 2's complement arithmetic overflow occurred.

Example: To execute `if (A == B)`, the CPU subtracts B from A (`SUB A, B`). If they are equal, the result is 0, so the hardware sets the Z flag to 1. The next instruction `JZ Target` (Jump if Zero) checks the Z flag and jumps.

Historically, there have been two competing philosophies on how to design an Instruction Set.

⇒13.1 CISC (Complex Instruction Set Computer)

Goal: Minimize the number of instructions per program.

• Large instruction set (hundreds of instructions).
• Instructions are complex and take many clock cycles to execute (e.g., an instruction that multiplies numbers directly in memory without loading them to registers).
• Variable-length instruction formats.
• Requires a complex Microprogrammed Control Unit.
• Example: Intel x86.

⇒13.2 RISC (Reduced Instruction Set Computer)

Goal: Execute instructions as fast as possible (one instruction per clock cycle).

• Small instruction set. Only simple operations.
• Load/Store architecture: Only LOAD and STORE instructions can touch memory. All math must be done on registers.
• Fixed-length instructions (easy to decode).
• Uses a fast Hardwired Control Unit.
• Example: ARM (used in almost all smartphones and Apple Silicon Macs).

Unit 3 bridges the gap between hardware execution and assembly programming.

⇒14.1 University Exam Checklist

• Write an assembly program to evaluate $X = (A + B) \times (C + D)$ using 3-address, 2-address, 1-address, and 0-address instructions.
• Explain Implied, Immediate, Direct, Indirect, and Indexed addressing modes with examples.
• Why is Relative Addressing useful? (Position Independent Code).
• Write the Register Transfer Language (RTL) for the Fetch cycle.
• Explain the difference between a Branch instruction and a Call instruction.
• Compare and contrast RISC and CISC architectures across at least 5 parameters.

⇒14.2 Systems Interview Focus

• Understanding that pointers in C are a direct high-level abstraction of Indirect Addressing.
• Why the industry shifted from CISC to RISC for mobile devices (RISC consumes significantly less power due to simpler decoding hardware).