Field effect transistors and amplifiers notes — Unit 3

While the Bipolar Junction Transistor (BJT) is a current-controlled device (Base current controls Collector current), the Field Effect Transistor (FET) is a purely Voltage-Controlled device.

⇒Why 'Unipolar' and 'Field Effect'?

• Unipolar: Unlike the BJT which relies on both electrons and holes, current in a FET is carried entirely by ONLY ONE type of majority carrier (either just electrons OR just holes).
• Field Effect: The current flowing through the device is squeezed or expanded by an invisible Electric Field generated by an external voltage applied to the 'Gate' terminal.

⇒BJT vs FET: The Ultimate Showdown

The Junction Field Effect Transistor (JFET) is the simplest type of FET. It consists of a solid block of semiconductor acting as a conductive pipe (the Channel), with two impurity regions diffused into the sides to act as a valve.

⇒N-Channel JFET Construction

• Source (S): The terminal where the majority carriers (electrons) enter the channel.
• Drain (D): The terminal where the electrons exit the channel.
• The Channel: A solid bar of N-type silicon connecting the Source to the Drain. Current easily flows through it.
• Gate (G): Two heavily doped P-type regions diffused into the sides of the N-channel. They are internally wired together. They form two P-N junctions with the channel.

⇒The P-Channel JFET

The exact opposite. A solid bar of P-type silicon (holes carry the current) with N-type Gate regions diffused into the sides.

To operate an N-channel JFET, we apply a positive voltage to the Drain (VDS) to pull electrons up the channel. Crucially, we apply a NEGATIVE voltage to the Gate (VGS) relative to the Source.

⇒The Pinch-Off Mechanism

• 1. VGS = 0V: The Gate is unpowered. The P-N junctions have a natural, tiny depletion region. The N-channel is wide open. A massive Drain Current (ID) flows. The JFET is a 'Normally ON' device.
• 2. Applying Negative VGS: As we apply a negative voltage to the P-type Gate, the P-N junctions become heavily Reverse Biased.
• 3. The Squeeze: A reverse bias forces the Depletion Regions to expand massively into the N-channel. Since the depletion region lacks free electrons, it acts as an insulator. The physical width of the conductive channel is literally squeezed thinner by the invisible electric field.
• 4. The Pinch-Off Voltage (Vp): If we make VGS negative enough (e.g., -4V), the two expanding depletion regions touch each other in the middle. The channel is completely choked off. Drain Current drops to Zero.

The behavior of a JFET is modeled using two crucial graphs: The Drain (Output) Characteristics and the Transfer Characteristics.

⇒Drain Characteristics (ID vs VDS)

Plotted for various fixed values of VGS.

• Ohmic Region: At very low VDS, the JFET acts like a simple voltage-controlled resistor. ID rises linearly.
• Saturation (Active) Region: As VDS increases, the depletion region near the drain becomes wedge-shaped and chokes the current to a constant maximum value. The current becomes totally flat and independent of VDS. (This is where amplification happens).
• Breakdown Region: Extreme VDS destroys the junctions.

⇒Transfer Characteristics (ID vs VGS)

Shows exactly how the Gate voltage chokes the Drain current. It is defined by Shockley's Equation:

ID = IDSS * (1 - (VGS / Vp))^2

Where:
ID = Actual Drain Current
IDSS = Max Drain Current (when VGS = 0V)
VGS = Applied Gate-Source Voltage (Must be negative)
Vp = Pinch-off voltage (The cut-off point)

This parabolic (squared) relationship proves that the JFET is a non-linear device, unlike the perfectly linear BJT.

The JFET has one major limitation: You can ONLY apply a Reverse Bias to the Gate. If you accidentally forward-bias it, a massive gate current flows, destroying the high input impedance.

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) solves this by placing a physical sheet of insulating glass between the Gate and the Channel.

⇒The MOSFET Architecture

• Substrate (Body): A large foundational block of lightly doped P-type silicon.
• Source and Drain: Two heavily doped N+ regions infused into the top of the substrate.
• The Oxide Layer: An incredibly thin, microscopic layer of Silicon Dioxide (SiO2) glass grown directly over the channel area. It is a perfect insulator.
• The Gate: A metal (or polysilicon) plate deposited exactly on top of the glass oxide layer.

MOSFETs come in two distinct flavors. The first is the Depletion-Type. In a D-MOSFET, the manufacturer physically diffuses an N-type channel connecting the Source and Drain during fabrication.

⇒Working Principle

Because the physical channel already exists, the D-MOSFET is a 'Normally ON' device, exactly like a JFET.

• Depletion Mode (Applying Negative VGS): A negative gate voltage repels electrons out of the channel, pushing them deep into the P-substrate. This 'depletes' the channel of charge carriers, squeezing the current down to zero (Pinch-off).
• Enhancement Mode (Applying Positive VGS): Unlike a JFET, we CAN apply a positive voltage! A positive gate voltage attracts extra free electrons from the P-substrate UP into the channel, enhancing it. The current rises vastly higher than IDSS.

⇒The Dual Personality

The D-MOSFET is unique because it is the only transistor that can operate in both depletion mode (negative voltages) and enhancement mode (positive voltages) smoothly crossing the zero-volt line.

This is the most important transistor in human history. Almost every CPU, RAM chip, and smartphone processor is built entirely out of billions of microscopic E-MOSFETs.

⇒The Architecture

Unlike the D-MOSFET, the E-MOSFET is manufactured with NO physical channel. The Source (N+) and Drain (N+) are completely separated by the P-type substrate.

Because there is no channel, if VGS = 0V, absolutely zero current flows. It is a Normally OFF device. It acts as a perfect open switch.

⇒Creating the Virtual Channel

• We apply a strongly Positive voltage to the Gate.
• The Metal-Oxide-Semiconductor acts exactly like a Capacitor. The positive Gate acts as the top plate, pulling a massive electric field through the glass oxide.
• This field violently repels the holes in the P-substrate downwards, and forcibly attracts minority electrons upwards, packing them tightly against the underside of the glass.
• Once the voltage reaches the Threshold Voltage (VT), enough electrons have gathered to form an artificial, 'Inversion Layer' N-channel connecting the Source and Drain.
• The switch is now ON! Current flows freely.

Because it has no physical channel, the mathematical behavior of the E-MOSFET is entirely dependent on surpassing the Threshold Voltage (VT).

⇒Transfer Characteristics (ID vs VGS)

• If VGS < VT : The device is totally OFF. ID = 0.
• If VGS > VT : The virtual channel forms, and ID begins to rise exponentially.

ID = k * (VGS - VT)^2

Where:
k = A device-specific constant based on geometry (Width/Length)
VT = The minimum voltage required to form the inversion layer channel.

⇒Why is it the king of Digital Logic?

Because it is 'Normally OFF' and draws strictly zero gate current, an E-MOSFET consumes practically ZERO electrical power when it is sitting idle waiting for a signal. A CPU with 10 billion BJTs would instantly melt from the base currents alone. A CPU with 10 billion E-MOSFETs runs cool.

If E-MOSFETs are so efficient, how did we make them even better? By pairing an N-channel E-MOSFET (NMOS) with a P-channel E-MOSFET (PMOS) to create CMOS: Complementary Metal-Oxide-Semiconductor.

⇒The CMOS Inverter (NOT Gate)

The fundamental building block of all digital logic. We stack a PMOS transistor on top of an NMOS transistor. Their gates are wired together as the Input. Their drains are wired together as the Output.

VDD (+5V)
 |
[PMOS] (Turns ON with a Logic 0)
 |----------- Output
[NMOS] (Turns ON with a Logic 1)
 |
GND (0V)

⇒The Magic of CMOS

• Input is 1 (+5V): The NMOS turns ON, pulling the Output to Ground (0). The PMOS completely turns OFF, blocking VDD.
• Input is 0 (0V): The NMOS turns OFF, blocking Ground. The PMOS turns ON, connecting the Output directly to VDD (1).

Notice that at NO POINT are both transistors ON at the same time. There is NEVER a direct path from VDD to Ground. The steady-state power consumption of CMOS logic is absolutely ZERO. Power is only consumed for a nanosecond during the switching transition.

Just like BJTs, FETs can be used as linear amplifiers (mostly in high-end audio equipment or radio receivers due to their low noise and high input impedance). To do this, we must bias them into the Saturation (Active) region.

⇒JFET Self-Bias Circuit

Unlike BJT voltage-divider bias, a JFET requires a NEGATIVE gate-to-source voltage (VGS). We achieve this brilliantly using just a source resistor (RS), without needing a dual-polarity power supply.

• The Gate is tied to ground via a massive resistor (RG ~ 1MΩ). Since IG = 0, the voltage drop across RG is zero. Therefore, VG = 0V.
• Drain current (ID) flows through RS, raising the Source voltage above ground: VS = ID * RS.
• VGS = VG - VS = 0 - (ID RS) = -(ID RS).
• The required negative bias is automatically generated by the transistor's own current!

⇒Common Source (CS) Amplifier

The FET equivalent of the BJT Common Emitter amplifier. Input to Gate, Output from Drain. It provides excellent voltage gain and an 180° phase inversion.

To calculate the AC voltage gain of a FET amplifier, we use an AC equivalent circuit, just like we did with the BJT's 're' model.

⇒Transconductance (gm)

In a BJT, Beta (β) linked input current to output current. Since a FET has no input current, we use Transconductance (gm), which links the Input VOLTAGE to the Output CURRENT.

gm = Change in Drain Current / Change in Gate Voltage
gm = ΔID / ΔVGS
Units: Siemens (S) or Mhos (A/V)

⇒The AC Equivalent Circuit

• The input side between Gate and Source is literally an OPEN CIRCUIT, representing the infinite input impedance.
• The output side is modeled as a Voltage-Controlled Current Source pushing a current of (gm * vgs) downwards.

⇒Voltage Gain (Av) of a CS Amplifier

v_out = - (gm * vgs) * (RD || rd)
v_in = vgs

Av = v_out / v_in = - gm * (RD || rd)

Where RD is the external drain resistor, and rd is the internal channel resistance.

FET amplifiers can be wired in three configurations, mirroring the BJT.

⇒The Source Follower (Common Drain)

Just like the BJT Emitter Follower, the Source Follower provides a voltage gain slightly less than 1. Its output perfectly mimics the input voltage wave. Its entire purpose is to provide massive impedance transformation—taking a weak signal from a high-impedance sensor and driving a heavy, low-impedance load without losing signal voltage.

While E-MOSFETs are computationally superior, their physical architecture hides a catastrophic physical vulnerability.

⇒The Glass Fragility

The Silicon Dioxide (SiO2) glass layer separating the Gate from the channel is insanely thin—often only a few dozen atoms thick. Because the Gate draws no current, any static electrical charge that builds up on the Gate pin has nowhere to escape. It acts as a tiny capacitor.

⇒Static Discharge (ESD)

If you walk across a carpet, your body can build up 5,000 Volts of static electricity. If you touch the Gate pin of a MOSFET, that massive voltage spikes across the microscopic glass layer.

The electric field becomes so intense that it literally punches a microscopic hole straight through the glass, physically fusing the Gate to the Channel. The transistor is instantly and permanently destroyed.

• This is why computer components (RAM, GPUs) are shipped in anti-static bags.
• Engineers must wear grounded anti-static wrist straps when handling bare MOSFETs.
• Modern commercial MOSFETs have built-in back-to-back Zener diodes internally clamped to the Gate pin to safely route static spikes to ground before they hit the glass.

⇒End-of-Unit Verification

• Explain why a FET is called a 'Unipolar' and 'Voltage-Controlled' device.
• Draw a comparative table listing 5 major differences between BJTs and FETs.
• Explain the 'Pinch-off' mechanism in an N-Channel JFET and why VGS must always be negative.
• Write Shockley's Equation for JFET transfer characteristics and sketch the parabolic curve.
• Draw the physical structure of a MOSFET and highlight the role of the SiO2 layer in creating infinite input impedance.
• Explain the exact difference in physical channel construction between a Depletion MOSFET (D-MOSFET) and an Enhancement MOSFET (E-MOSFET).
• Describe how an 'Inversion Layer' creates the virtual channel in an E-MOSFET.
• Draw the schematic for a CMOS Inverter (NOT Gate) and explain why it consumes zero steady-state power.
• Define Transconductance (gm) and state its unit.
• Draw the AC equivalent small-signal model of a FET and derive the voltage gain formula `Av = -gm * RD` for a Common Source amplifier.
• Explain why bare MOSFETs are easily destroyed by static electricity (ESD).